A fractional-N clock generator is an integral component of wireline and wireless systems. For acceptable noise performance, a fractional clock can be generated using inductance-capacitance (LC)-based fractional-N phase locked loops (PLLs). LC-based fractional PLLs, however, consume a large implementation area within an integrated circuit (IC). As such, LC-based fractional PLLs are not well-suited for deep sub-micron ICs. On the other hand, ring voltage controlled oscillator (VCO)-based fractional PLLs consume less implementation area than LC-based fractional PLLs, but have worse noise performance. It is therefore desirable to provide a fractional-N oscillator circuit that both conserves implementation area and exhibits acceptable noise performance.